In fabrication of semiconductor chips, various processing steps are carried out simultaneously on a single wafer to produce the desired semiconductor Integrated Circuit (IC). Typically, ICs are produced in large batches on a single wafer of Electronic-Grade Silicon (EGS) or other semiconductor material through the processes such as photolithography. The wafer is cut (“diced”) into many pieces, each containing one copy of the circuit. The process of cutting the wafer is called dicing or singulation and each piece is called a die or chip.
During the singulation process, it is necessary to protect the chips from damage, as isolation of individual chips from wafer may cause damage to the chips. To protect a chip and to reduce such damage, normally an adhesive tape is first applied to the bottom surface of the wafer before singulation. After the singulation process, the adhesive tape is removed from the chip. Removal of an adhesive tape from a thin die (for example, of minimum thickness 40 μm) is subjected to die cracking and results in production loss. Various methods have been attempted in prior arts to overcome this problem.
In a US patent application US 2009/0101282 A1, an apparatus and method for picking-up a semiconductor die is disclosed. The apparatus and method uses a wiper that has a tip end moving in and out of an adherence surface of a die stage and a shutter that is moved with the wiper while blocking a suction window formed in the adherence surface. When picking up a semiconductor die, the tip end of the wiper is aligned with a first end of the die, the wiper is moved along the adherence surface while the tip end of the wiper is protruded from the adherence surface with the die being suction-held by a collect. A suction opening is sequentially opened between a first end surface of the suction window and a seat surface of the wiper as the wiper is moved, and a dicing sheet attached to the die is suctioned into the suction opening that has been opened and sequentially peeled off from the die. In this art, the wiper sliding speed must be slower than the propagation speed of the delamination process and the delamination process has to propagate from one side to another. Therefore, the circle time is limited.
U.S. Pat. No. 7,238,258 discloses a system for peeling semiconductor chips from a tape. The system is provided with a nose on a housing. The nose has transverse dimensions smaller than the transverse dimensions of a target chip. Apertures are provided through the nose from the housing. Vacuum ports are provided in the housing adjacent the nose. A vacuum source controllably connects to the apertures and the vacuum ports. The nose is positioned adjacent to a tape attached on the side opposite to the target chip. Vacuum is applied to attract the tape against the nose and the adjacent portions of the housing to peel the tape from the peripheral edges of the target chip while supporting the tape in the center of the target chip.
In this prior art, the vertical ejection tools include push-up needles and push-up two staged blocks. Since all the needles are moved simultaneously, it creates a high pressure at the center of the chip before it is peeled, thus increasing the likelihood of the chip to be damaged. Additionally, the angle between the slanting tape and the chip surface is small, which may lead to reduced process flows and ejection sequences.
A need, therefore, exists for an improved system and method for peeling a semiconductor chip from a tape that overcomes the above drawbacks.